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Author: Che-Chang Yang(2006-08-27); recommendation: Yeh-Liang Hsu (2006-09-01).
Note: This article is Chapter 3 of Che-Chang Yang’s Master thesis “Development of a Portable System for Physical Activity Assessment in a Home Environment.”

Chapter 3. Design of the Distributed Data Server

This chapter describes the design of the Distributed Data Server (DDS), which consists of a PIC_ SERVER v3 and a standard peripheral application board (PAB).

3.1     PIC_SERVER v3

PIC_SERVER v2 based upon PIC18F452/4620 microcontroller (Microchip) has been used in a variety of design applications. For the increasing needs of more I/O channels and package integration, a new PIC_SERVER v3 based upon PIC18F6622/6722 microcontroller was developed in place of PIC_SERVER v2. Major features of the PIC_ SERVER v3 are:

(1)   Using PIC18F6X2X microcontroller

The PIC18F6X2X series which include PIC18F6527, PIC18F6621, PIC18F6622, PIC18F6627 and PIC18F6722 are in 64-pined TQFP. Compared with PIC18F4620 (P-DIP), the chip size of a PIC18F6X2X is reduced significantly while the number of I/O channels is larger. PIC18F6X2X has two RS-232 serial channels, which is another major advantage over PIC18F4620. Table 3.1 is a simple comparison of the major specifications between PIC18F4620 and PIC18F6722.

Table 3.1 Specifications of PIC18F6722 and PIC18F4620

 

PIC18F6722

PIC18F4620

Package

64-pin TQFP

40-pin DIP, 44-pin TQFP

Size(L×W×H, mm)

12×12×1.1

34.67×7.87×3.81

Program Memory

(bytes)*

Flash

128K

64K

Single-Word Instructions

65536

32768

DATA Memory (bytes)

SRAM

3936

3986

EEPROM

1024

1024

I/O pins

54

36

10 bit A/D (ch)

12

13

CCP/ECCP (PWM)

2/3

1/1

Timers 8/16-bit

2/3

1/3

(2)   Built-in RTL8019AS Ethernet controller

In PIC_SERVER v2, the Network Interface Controller (NIC) using a RTL8019AS Ethernet controller is an external module. In PIC_SERVER v3, this Ethernet controller along with an EEPROM chip is integrated together onto the same PCB. The memory capacity of the EEPROM is enhanced from 256kB to 512kB or 1MB.

(3)   PCB miniaturization

Most of the parts of PIC_SERVER v3 are in SMD packages. With less vias needed in the PCB and reduced size of each part, the layout density (part placement and track routing) can be increased, which effectively reduces the size of the PCB.

Figure 3.1 to Figure 3.4 shows the schematics of a PIC_SERVER v3. Table 3.2 is the BOM list of PIC_ SERVER v3. Two RJ45 connectors (P02-102-11A9 and P65-P01-11A9, SpeedTech) can be used in this model. The later one is preferable for the built-in LED (TX and RX status) indicators.

Figure 3.1 Schematic I (PIC18F6X2X)

Figure 3.2 Schematic II (RTL8019AS)

Figure 3.3 Schematic IIIConnectors and EEPROM

Figure 3.4 Schematic IVRJ-45

Table 3.2 BOM list of PIC_SERVER v3

Part

Serial number

Spec.

Amount

Package or notes

PIC

U1

PIC18F6X2X

1

64-Lead P-TQFP

Ethernet controller

U2

RTL8019AS

1

100-Lead QFP

EEPROM

U3

24LC512/1025

1

8-lead Plastic SM-Medium, 208 mil(SOIC)

Crystal oscillator

Y1

10MHz, 20/30ppm

1

HC-49 SMD/DIP

Y2

20MHz, 20/30ppm,

1

Resistor

R1

100W

1

0805

R2~R8

2.2kW

5

R9

10K

1

Capacitor

C1, C2

22pF

2

0805

C4, C5,C6

0.22mF(224)[1]

3

C7, C8,C9

0.1mF(104)

3

C3

0.01mF(103)

1

LED

D1

*

1

SYS_LED

Connector

J1, J3

SIP20

2

CN1, CN3

JP1

IDC16

1

CN2

J2

RJ45(Tab down)

1

P02-102-11A9

P65-P01-11A9

The PCB size of PIC_SERVER v3 is 40mm×80mm. Figure 3.5 shows the part placement, and Figure 3.6 shows the track routing. All parts are on the top layer except the RJ45 connector. Tracks linking up the bypass capacitors are as short as possible for a better noise shunting effect. The track lengths of the A/D channels are also as short as possible and are separated from the area of digital I/O channels to avoid noise contamination. Track vias, especially those near the SMD pads, are covered with solder masks to avoid short-circuits. Figure 3.7 shows the finished product of PIC_ SERVER v3 of which overall size is 40mm×85mm×15mm.

Figure 3.5 PCB part placement

Figure 3.6 PCB Layout (track routing, top layer and bottom layer)

Figure 3.7 PIC_SERVER v3 finished product

3.2     Design of the peripheral application board

PIC_SERVER v3 is a controller module with Internet capability. With only external power supplied, it can operate as a web server. The purpose of the peripheral application board is to provide an expanded platform for PIC_SERVER v3 for data acquisition, processing and storage. Combining the PIC_SERVER v3 and the PAB, the DDS is the core component in the PTMS structure.

Figure 3.8 to Figure 3.13 are schematics of all the circuit sections in a PAB. Table 3.3 is the BOM list. For the power section shown in Figure 3.8, three low dropout voltage regulators LM2940/LM3940 are used instead of the LM78XX series for lower heat generation. Two LM2940 voltage regulators generate stable +5V DC power output from 6.25V up to 26V DC input. One is for main ICs and the other for LCD backlight. 3.3V power from a LM3940 voltage regulator is for MMC. In addition, unregulated input bypass power, regulated +5V and +3.3V power are also available from the SIP pocket CN4 (J6) power bank (Figure 3.9). D2 and D3 LEDs are indicators of power and RJ45 link status, respectively. If the net cable (CAT5) is disconnected, the D3 indicator will go out.

Figure 3.9 shows the connector. CN5 (J7) is the main 19-port I/O bank with up to 8 analog A/D input channels and 3 CCP ports. JP2 and JP3 are I2C ports and JP4 is for LCD text panels or an external keyboard (digital input). J6 (CN4) and J8 (CN6) are a power bank and a GND bank, respectively. J4 (CN1), J5 (CN3) and JP1 (CN2) are for the connection to PIC_ SERVER r v3. Figure 3.10 shows the schematic of MMC built-in on PIC_ SERVER v3.

Figure 3.11 is the RTC (real-time clock) schematic. Two power +5V from the voltage regulator and +3V from a battery are both connected to it. If the +5V power is shut down, the battery will still provide power to the RTC to avoid any errors occurring for data storage. In addition, the battery power can be monitored via AN0 (RA0) in CN5. This function can be disabled by removing the jumper JP5. In addition to the RESET (S1) and ICP bottoms (S2), two buttons (S3 and S4) and a switch selector (J3) shown in Figure 3.13 are also available for any programmed uses. By voltage levels of +5V, +2.5V and 0V in J3, three modes can be selected.

Figure 3.8 Schematics (I)

Figure 3.9 Schematics (II)

Figure 3.10 Schematics (III)

Figure 3.11 Schematics (IV)

Figure 3.12 Schematics (V)

 Figure 3.13 Schematics (VI)

Table 3.3 BOM list of the PAB

Part

Serial number

Spec.

Amount

Note

DC power jack

J1

 

1

DC 6.25V-26V

Power switch

J2

 

1

 

Switch

J3

 

1

SNAP3 SW

SIP

J4,J5,

20 pin

2

CN1,CN3

SIP socket

J6,J7,J8

20 pin

3

CN4,CN5,CN6

JP1

8×2 pin

1

CN2

JP2, JP3

4×2 pin

2

I2C

JP4

7×2 pin

1

LCD

JP5

2 pin

1

JUMPER

Battery

BT1

 

1

3V Lithium Battery

Beeper

LS1

HS-1206A

1

 

RJ-11 connector

J9, J10

6P6C

2

RS-232A, RS-232B

Inductor

L1

10uH

1

 

Resistor

R1,R2

2.2kW (1k)

2

0805

R12

200W

1

R3,R5,R7,R9,R10,R11

10kW

6

R4,R6,R8

20kW

3

R13~R18

1 kW (2.2k)

4

Diode

D1

1N5401/5404

1

 

LED

D2,D3

SMD

 

0805

Capacitor

C1,C3,C5

0.22/0.47uF

3

 

C2,C4,C6

47uF~100uF

2

no less than 22uF

C7

1uF

1

1206

C8,C9

22pF

2

0805

C10~C13

0.1uF

4

0805

Voltage regulator

U1,U2,U3

LM2940,LM2940,

LM3940

3

TO-220

Memory card

U4

MMC

1

 

RTC

U5

DS1320

1

 

RS-232 connector

U6

MAX232

1

 

Crystal oscillator

Y1

32.768kHz

1

3mm×8mm

Bottom

S1,S2,S3,S4

 

4

RESET,ICP

B1,B2

Figure 3.14 illustrates the PCB part placement of the PAB. The PCB size is 86mm×136mm. All the resistors and capacitors are in SMD type. Figures 3.15 and 3.16 show the PCB track layouts, and Figure 3.17 indicates the I/O port arrangement. Signal I/O ports (CN5), power port (CN4) and GND port (CN6) are aligned together for convenient use. Figure 3.18 shows the finished product of PAB, and Figure 3.19 shows the complete DDS setup.

Figure 3.14 PCB part placement

Figure 3.15 PCB layout (top layer)

Figure 3.16 PCB layout (bottom layer)

Figure 3.17 I/O ports description

Figure 3.18 Finished product of PAB

Figure 3.19 Complete DDS set